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AD9364 DC-OFFSET issue

Question asked by jarod0523 on Mar 9, 2018
Latest reply on Mar 19, 2018 by jarod0523

Recently I'm working on a project with AD9364.

We  plan to use  AD9364 to recieve a modulated narrow-band signal (AM  Amplitude Modulation, carrier frequency =245MHz, 1KHz single tone is modulated to  the carrier  ). We choosed FPGA to do the AM demodulation part.

We use signal generator to generate  RF to 245MHz (only carrier without modulation),set LO to 245MHz (=RF).Thus the data of I channel P0D is as follow:

P0D data of i channel

the data of Q channel P1D is as follow:

P1D_Q_data

Then set the generator AM modulation(1KHz tone) on ,the result data of demodulation is as follow:

demodu_data_8KHzsamplerate

But when i change the RF carrier (without modulation ) to 245.01MHz,LO is still 245MHz (10KHz offset),the data of I & Q channel  is as follow:

I&Q_data

It looks perfect.

And the result data of demodulation is as follow,demodu_data_8KHzsamplerate_10khzoffset

Looks much better ~~~

I wonder why  it has two different results. Does the DC-offset affect the RX chain performance?

If we insist on the first way (RF=245MHz,LO=245MHz),how can i make it right? Which registers do i need to config?

Thank you  so much~

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Sorry about my  poor english ,wish it wouldn't  make you confused!   ^_^!!

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