when I look up AD9361 Reference Manual, AXI_AD9361AXI_AD9361[Analog Devices Wiki]
and the schematic diagram of AD9361, part of which is shown below,
there are lots of clock such as IP_reference_clk for AXI_AD9361, DATA_clk(tx_clk_out), TX_sample_clk(which is marked with blue block in schematic diagram) and DAC_sample_clk. And I find IP_reference_clk equal to 244MHz and TX_sample_clk equal to 61.44MHz default, where whether transmit signal is decimated by a factor of 4. And next question is what relation is between IP_reference_clk and DATA_clk. Last question is whether IP_reference_clk can be charged, if yes, how to control it if I have the no-OS platform for AD9361?
Thanks in advance,