Sorry if this question is due to a misinterpretation of manuals, but it's not clear for me.
I'm trying to use the HADC and I need a conversion rate of 50.000 values per second in the four channels.
I know that, as the HW reference manual says: "The HADC takes 20 cycles of fSAMPLE for one channel conversion" and "Select fCLK and HADC_CTL.FDIV values so that fSAMPLE is in the range of 50 kHz to 22.5 MHz". So, I think I need a fSAMPLE of 4 MHz.
But the FDIV field is just 4 bit-long (0<FDIV<16) and fCLK is SYSCLK0, usually 100MHz (isn't it?), so I cannot get this fSAMPLE without changing the SYSCLK0.
Are all my premises true?
If I have to program SYSCLK0 to , e.g. 50MHz, the rest of peripherals will operate with this clock rate and this would not be desirable for me.