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AD9914 SYNC_CLK Amplitude

Question asked by jferment on Mar 7, 2018
Latest reply on Mar 9, 2018 by KennyG



We are using a AD9914 in SPI mode and providing an external differential reference generated from a PLL.


The goal is to run the DDS at 3.5GHz.


Essentially we are trying to switch frequencies using the Profile select and IO_Update pins.  We are trying to Synchronize these to a SYNC_CLK as the data sheet specifies the "MUST BE SETUP ON THE RISINGE EDGE OF SYNC_CLK"


At a 1GHz input REF_CLK  then SYNC_CLK is 3.3V however its not a 50% duty cycle square wave or even a sinusoid, its more like a bad triangle.


At a 3.5GHz input SYNC_CLK amplitude olny changes from 0.3V to 0.8V..........hardly enough to be used with a 3.3V CMOS input.


We experienced similar behavior across multiple parts and even on the evaluation board.


Is this a KNOW PART PROBLEM?  Is there a work around?


There are several threads describing the same problem but i have yet to find the actual resolution


the closest thread to explain the problem is AD9914 Data Sheet discrepancies? 


However the thread seems to die and no one provides an actually response as to why SYNC_CLK amplitude is low.