I am working with AD9371 and JESD PRBS system: my target is validating the JESD link if possible both on the serializer level and on JESD framer.
To validate the JESD framer level I want to implement the PRBS generator\checker within the FPGA.
In the AD9371 example design the documentation of the IP axi_ad9371 report a PRBS generator\checker within the hdl code
I have look through the code to find the hdl PRBS generator\checker but I didn't find any.
I expect to find it in the file below around the input data selection mux (dac_data_sel_s)
1) Is there a PRBS generator\checker within the HDL code?