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Error using AXI JESD204 (jesd204_up_common.v:306)

Question asked by MateoConLechuga on Mar 5, 2018
Latest reply on Mar 26, 2018 by andrei_g

I have been trying to build the DAQ2 reference design for the KC705 using Vivado 2017.4 in the latest release ( hdl_2017_r1 ), and I am continuously getting a synthesis error 'module "up_clock_mon' not found in the referenced file in the title. I attempted to add it back from the common/ directory in the IP packager and it seems to have resulted in more errors. Am I using the right release?

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