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questions about AD9371 hdl reference design

Question asked by rosy2cloud on Mar 3, 2018
Latest reply on Mar 13, 2018 by AdrianC

Hi~

   I am using  adrv9371 hdl reference design on zc706, I want to add a customer IP1 in Tx chain and a customer IP2 in ObsRx chain,and the sample rate of IP1 is equal "clk_0"(dac_clk) of "axi_ad9371_tx_clkgen",the sample rate of IP2 is equal "clk_0"(adc_os_clk) of "axi_ad9371_rx_os_clkgen"

   in Tx chain of original hdl block design, "axi_ad9371_tx_dma"  receive Tx data from PS or DDR  Via AXI bus,then send to "axi_ad9371_fifo","util_ad9371_tx_upack","axi_ad9371_core","axi_ad9371_tx_jesd" , "util_ad9371_xcvr"  and "tx_data_0~3_p/n" in turn.I want to insert customer IP1 between "axi_ad9371_fifo" and "util_ad9371_tx_upack",but the output  "dac_data[127:0]" of "axi_ad9371_fifo" is 128 bit,and the 128-bit data have the following structure (MSB first):{TX2_Q_1, TX2_Q_0, TX2_I_1, TX2_I_0, TX1_Q_1, TX1_Q_0, TX1_I_1, TX1_I_0} (2 consecutive samples per channel),I want to comfirm  whether "dac_data[127:0]" sample rate is dac_clk/2? if right, I just need to change "dac_data[127:0]"@dac_clk/2 to dac_data_customer[63:0]@dac_clk,  and send  dac_data_customer to customer IP1.on the other hand,do I need to delay "dac_dunf" and "dac_xfer_out" for align?

   in ObsRx chain,after the process of "axi_ad9371_rx_os_jesd" and "axi_ad9371_core",the "adc_os_data_i0" are still 32bit,is it consist two consecutive samples?

  thanks!

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