I'm using a ZC702 with FMCOMMS3 ( AD9361 ) and made a FFT system in Simulink ( using the Simulink HDL FFT block and a FIFO ), but the system fails to build the bitfile- Vivado 2016.2 crashes
I followed the ADSB example as a base for my design ,
my information :
- ZC702 with FMCOMMS3
- Vivado 2016.2
- AnalogDevices FMCOMMS2/3 ZC702 (Rx) ( MathWorks_tools git branch 2017a )
- 3.1.1 Set Basic Options : Language : Verilog ( according to the user guide )
- all other settings from the ADSB demo
- I've run through Fixed point designer so no "doubles" remain
- using "...hdl_prj\vivado_ip_prj\projects\scripts\adi_build.tcl" in 4.3 of HDL-WA
- The ADSB example builds the bitfile successfully with similar settings ( the only difference is in 1.3 : Target interface )
Vivado crashes with
Abnormal program termination (EXCEPTION_ACCESS_VIOLATION)
Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
I've also attached the .dmp , .log and runme.log files.
# An unexpected error has occurred (EXCEPTION_ACCESS_VIOLATION)
no stack trace available, please use hs_err_<pid>.dmp instead.
Is it possible to update the reference design to a newer version of Vivado ( like 2016.4 or 2017.2 ) if its an issue with Vivado 2016.2 ?