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FIR Sample Clock

Question asked by mclark on Mar 1, 2018
Latest reply on Mar 1, 2018 by travisfcollins

I'm working on the AD9361 and the No-OS driver. After using the AD9361 Filter Wizard, the number of FIR coefficients is always set to 32 @ 50MHz. From the AD9361 reference manual (Rx FIR pg 34), this implies the FIR sample clock is set to ADC_CLK/2. From the scenario described below, I should be able to support 64 coefficients. How can I set the FIR sample clock to ADC_CLK? I've reviewed the register map, but I'm having a difficult time locating it's control register. Thanks!