When I use AD9364, the clk of ADC is 245760000 Hz. I set the register of 0x00A is 0xfa , I get the 3.8MHz clk from the pin of clkout. So I consider my config is right.
Then I set the register of 0x003 is 0x5e . From this config, I consider Data_clk must 15.36MHz, But I real test from oscilloscope, the clk of Data_clk is 31MHz. Why the Data_clk is not same with my expectation？ The Data_clk is Rx_sample_clk?
the attachment is my wave of oscilloscope.