I am trying to do a loopback test within my FPGA in order to test some custom DSP blocks. I am having trouble figuring out the data format that is required for the deframer and what is coming from the framer.
I have read in the user guide that the DAC has 14bit resolution and that the upper 14 bits of the I and Q sample are used [15:2] and the lower 2 bits are unused [1:0]. Is this correct, can I just pad bits 0 and 1 with zeros?
My other question is regarding the framer. It looks like the ADC has 16bit resolution, is this correct or is the same as the DAC and I need to use upper or lower bits?