What is the maximum SPI baud rate and UART Baud rate using ADuCM4050? It looks like the maximum PCLK can be 52 MHz but does that translate to increased frequency for SPI and UART clocks.
A higher maximum PCLK frequency of 52MHz in ADuCM4050 does indeed translate in to a higher possible SPI clock (SPI_CLK) frequency and a higher possible UART baud rate.
1. Regards to maximum SPI_CLK frequency, please refer to the Timing Specifications section in the ADuCM4050 datasheet, where the specifications for SPIH (SPI2) correspond to a maximum possible SPI_CLK frequency of 26MHz, while those for SPI1 and SPI0 (SPI1 and SPI0 are collectively referred to in the datasheet, as just 'SPI') correspond to a maximum SPI_CLK frequency of 13MHz.
2. Regards to UART, the maximum theoretical baud rate does scale with PCLK frequency. So, for a PCLK frequency of 52MHz, the maximum UART baud rate that can be configured would be 13Mbps. However, the practical baud rate that can be achieved in a system, would generally be lower as UART is an asynchronous serial interface and a major determinant of the practical (error-free) baud rate that can be achieved is typically, the accuracy of the clock sources in the system. For a more detailed analysis of the UART baud rate, please refer to the FAQ below.
FAQ: "What is the highest UART baud rate that can be used while ensuring reliable communication?"
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