For the internal ADC of AD9874, what is the sampling rate? Is it sampling at the Fclk or the Fclk/8?

If the input IF is situated 15,75MHz, bandwidth is 3.3KHz, the output data rate is required at 16.8KHz, how to choose the LO and Fclk?ad9874

For the internal ADC of AD9874, what is the sampling rate? Is it sampling at the Fclk or the Fclk/8?

If the input IF is situated 15,75MHz, bandwidth is 3.3KHz, the output data rate is required at 16.8KHz, how to choose the LO and Fclk?ad9874

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**For the internal ADC of AD9874, what is the sampling rate? Is it sampling at the Fclk or the Fclk/8?**It's Fclk. The ADC sampling rate ,Fclk, is specified in the range of 13-26 MHz. The IF input of the ADC is specified at Fclk/8 thus can be in range of 1.625 to 3.25 MHz. The on-chip mixer is used to down-convert the AD9874’s input signal this IF range.

**If the input IF is situated 15,75MHz, bandwidth is 3.3KHz, the output data rate is required at 16.8KHz, how to choose the LO and Fclk?**The LO needs to be chosen such that the output of the mixer (and IF input to ADC) is centered between 1.625 to 3.25 MHz.

For this specific case, it may be possible to operate both the LO and Fclk at the same frequency of 18MHz. This example would give:

Mixer output = 18 MHz – 15.75 MHz = 2.25 MHz

ADC IF input=Fclk/8 = 18 MHz /8 = 2.25 MHz

To do that, you could use one of the following two options:

- Use digital fractional resampler to convert to 16.8 KSPS. The AD9874 provides factors of 48 or 60 for decimation factors so you could select one of the decimation factors that simplifies fractional resampler. For example, if you set decimation factor to 900 (K=1, M=14), the output sample rate would be 20 KSPS. You could use a fractional resampler that provides up/down sampling ratio of 21/25 to convert 20 KSPS to 16.8 KSPS. This method still allows one to use common 18 KSPS clock for LO and CLK.
- Set Decimation factor to 960 (K=0, M=15) such that ADC clock is in the 16.128 MHz MHz which results in an ADC IF input of 2.016 MHz. The LO for mixer would be set to 15.75+/-2.016 MHz depending on high or low side injection.

Method 1 would be more elegant of a solution.

I think there was a miscommunication. The ADC samples at Fclk, not Fclk/8. After that, the decimation filter does all the converting.