I am working on HDL part of AD9371 . I am able to compile the HDL code for zynq ultrascale+ which is present on
https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1 . When I go through the code I realised that all the AXI register values are initialized to zero. Are there any initialization file or API which will initialize these AXI register value of PL ?