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AD9371 PL AXI register configuration

Question asked by Rahul1004 on Feb 28, 2018
Latest reply on Mar 2, 2018 by andrei_g

I am working on HDL part of AD9371 . I am able to  compile the  HDL  code for zynq ultrascale+ which is present on

https://github.com/analogdevicesinc/hdl/tree/hdl_2017_r1 . When I go through the code I realised that  all the AXI register values are initialized to zero. Are there any initialization file or API which will initialize these AXI register value of PL ?

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