My company is designing acquistion board and we targeted AD9253 as its ADC. We will use FPGA to configure ADC and PLL and to retreive data from it. Due to the limit of available pins on our FPGA I want to minimize interfaces as much as possible.
I read AD9253 datasheet and I don't understand if SDIO and SCK pins can be shared among AD9253 and other devices(for example AD9510). I also read AN-877.
SDIO and SCK pin have other function when not used in SPI mode.
AD9253 in SPI mode
AD9253 has its own CSB pin(not shared ) ; lets call it ADC_CSB
AD9510 has its own CSB pin(not shared ) ; lets call it PLL_CSB
SCK shared between AD9510 and AD9253
SDIO shared between AD9510 and AD9253
If ADC_CSB is set temporary set high and PLL_CSB set low, and SDIO and SCK data streamed to write/read to/from AD9510.
Will that data on SDIO and SCK signals be interpreted as OLM and DTP(Lane pin setting and digital test pattern settings) in ADC?