AnsweredAssumed Answered


Question asked by s.kannan on Feb 26, 2018
Latest reply on Feb 26, 2018 by mhennerich

I have AD9364 with Picozed PZSDRCC-BRK. I'm testing it with IIO Osc application, when the register settings for digital interface is 0x10=0xC8; 0x11=0x00; 0x12=0x02(CMOS full duplex mode), I'm getting the correct data at Rx end(snapshot attached below)

But, when I tried for LVDS mode with the register settings 0x10=0xC8; 0x11=0x00; 0x12=0x10(LVDS full duplex mode) I'm not getting anything even in Rx.

What went wrong?

Do I need to change any more settings?

My ensm  is in TDD Dual synth mode and I'm feeding the signal from SFU to Rx port A.