Disclaimer: I'm not an expert - do not make any assumptions of what I should know.
I'd like to create support for ZC702+FMCOMMS3 in Vivado 2016.4, to be used in the HDL Coder Workflow Advisor (HDLWA) (MATLAB R2017b).
I generated a Vivado project from source files using this repository. I made some changes to the project in an iterative process. Changes include: renaming blocks, rerouting signals - nothing major. During each iteration I generated a tcl file from the block diagram, tested it in the HDLWA, and made necessary changes to the tcl file if errors occurred (i.e., I generated the project from the tcl file, made necessary changes, exported to a tcl, and used the newly generated tcl in HDLWA).
Here's the problem. When I try and synthesize/implement the updated project it gives the following error:
[Place 30-415] IO Placement failed due to overutilization. This design contains 284 I/O ports while the target device: 7z020 package: clg484, contains only 200 available user I/O. The target device has 330 usable I/O pins of which 130 are already occupied by user-locked I/Os. To rectify this issue: 1. Ensure you are targeting the correct device and package. Select a larger device or different package if necessary. 2. Check the top-level ports of the design to ensure the correct number of ports are specified. 3. Consider design changes to reduce the number of I/Os necessary.
The original project can be synthesized/implemented. The changes I made weren't very significant, yet it seems like the FPGA is now overutilised. The Sources -> Hierarchy of the two designs do seem quite different (Left: changed project. Right: original project):
Why is the hierarchy so different? Also, I noticed that the changed project does not have a top module, what is the implication of this? What should I do to correct the error?
I've attached both the changed (system.tcl) and original (system_orign.tcl) project's tcl file.
Thank you in advance,