I need help designing with ip cores for different purposes like FFT core designing etc.
You are a bit vague in your question. Is this in any way related with our reference designs ?
If not, we don't provide support for generic IP design. I think Xilinx / Intel documentation and forums will help you better.
I want to design FIFO core and then want to instantiate it into my top module of verilog how i can done it?
I think this type of questions you can answer by simply googling it (Verilog: How to instantiate a module - Stack Overflow). We don't support generic Verilog design on this forum. Going through a verilog tutorial may be the right place to start, maybe one offered by your specific FPGA vendor.
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