AnsweredAssumed Answered

Please inform us about DPLL

Question asked by bokyung on Nov 30, 2011
Latest reply on Dec 6, 2011 by DaveD

I have used is ADV7611 chip.

 

Looking at the data sheet(DPLL 0xA0 reg)

 

CLK_DIVIDE_RATIO

 

This sets the ratio of reference clock to crystal. F(ref ) = F(xtal) * (clock ratio + 2).

0x0 forces automatic mode, in which F(ref ) is kept as close to 324MHz as possible using xtal_freq_sel[1:0] in IO map.

 

I have used the crystal(28.636363)  If you must use 0x0A calculated hearts.
But the CLK is the register values should be used to 0x0B.

 

And ADV chips were produced using a few of the board. However, by setting up some of the boards are using 0x0d.


I do not know what.

 

Please let us know... ADV7611 reg setting Reference value..

Outcomes