In my application I connected, due to limited resources, the parallel data port of two AD9915 to one port on a FPGA.
and use the function pins F0 to F3 to select each individual chip, which means they dynamically change their state.
In table 17 of the data sheet (Rev. F) for bit 17 of the CFR1 register it is noted that the function pins must meet the timing of
the SYNC_CLK edge. What exactly does that mean?
My application requires to set a frequency, amplitude and phase to both chips and modulate each value individually. At the moment this is done by parallel programming the values into the Profile 0 registers (0x0b and 0x0c). However there is a parallel data port enable (bit 22) in CFR2, which makes me believe there is a better way to this, but I couldn't figure out how exactly this bit is working. If this bit is set, to which address do I need to write the values?