There is a specification tSODM in data sheets.
But it seems that the table and the figure do not match.
ADAU1761 data sheet rev.C
Page 12 Table 7. Digital Timing
SERIAL PORT tSODM ( ADC_SDATA delay. Time from BCLK falling in master mode.)
Page 13 Figure 3. Serial Output Port Timing
( In the figure, the timing looks like setup time to BCLK rising edge. )
1. The table (delay) and the figure, which is a correct specification?
2. If specification is output delay, are there the specification in slave mode, too?
If I misunderstood above, could you please let me know.