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ADAU1361/1761 SERIAL PORT ADC_SDATA output delay timing specification.

Question asked by Euglena on Feb 23, 2018
Latest reply on Mar 1, 2018 by Euglena

There is a specification tSODM in data sheets.
But it seems that the table and the figure do not match.

 

ADAU1761 data sheet rev.C
http://www.analog.com/media/en/technical-documentation/data-sheets/ADAU1761.pdf

 

Page 12 Table 7. Digital Timing
SERIAL PORT tSODM ( ADC_SDATA delay. Time from BCLK falling in master mode.)
Page 13 Figure 3. Serial Output Port Timing

( In the figure, the timing looks like setup time to BCLK rising edge. )

 

1. The table (delay) and the figure, which is a correct specification?

2. If specification is output delay, are there the specification in slave mode, too?

 

If I misunderstood above, could you please let me know.

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