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Multiple AD9361 Transmission Phase Coherent

Question asked by zhoukai119 on Feb 22, 2018
Latest reply on Mar 12, 2018 by Vinod

#

Hi Experts,

Here is my application:
[1] Use EIGHT AD9361 to achieve 16 TX channel phase coherent Transmissions (Each AD9361 contributes 2 TX channels, TX1A and TX2A),no need RX. And the EIGHT AD9361 are connecting to one FPGA.

[2] Each AD9361 Tx frequency could be tuned independently within the AD9361 working frequency range (as wide as possible). For example, one AD9361 two channels transmitting at 1Ghz, and the second AD9361 two channels transmitting at 2Ghz....... and all their phases are coherent.

[3] Fixed skew (offset) between the 16 channels are allowed, but I hope after each time power on and alignment, the skew (offset) could be a set of relative fixed value between channels, not variable from power on to next power on, or the uncertainty is small enough to be ignored

 

I read below link
https://wiki.analog.com/resources/eval/user-guides/ad-fmcomms5-ebz/multi-chip-sync

 

What I learnt is to make multiple AD9361 Tx phase coherent, we should take care both RFPLL part and BBPLL part. And now I have some questions:


For the DAC part:
   [1] How should I take care about the BBPLL part which means the DAC sampling clock?
   [2] And I must do this step before LO alignment, right?
   [3] What is the sync accuracy for the SYNC_IN function?

 

For the LO part:
   [1] If I use "Internal LOs + FPGA" approach to align all 8 AD9361 Tx phase from outside at 100Mhz (this is not my working status), will it guarantee at another frequency points?
   [2] After the alignment, will it keep the phase coherent even after I change first AD9361 to 500Mhz, and the second AD9361 to 1Ghz, and the third AD9361 to 2Ghz,and ......... and all 8 AD9361 may working at same or all different frequencies, will the phase keep coherent in FDD mode?
   [3] If all 8 AD9361 XTALN share one common clock,and use internal RFPLL LO, will the 8 AD9361 RFPLLs locked and output at a fixed set of phase offset for each time power on lock? If true, I think there is no need to do the "Internal LOs + FPGA" alignment.

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