I am trying to better understand the ADC. The data in tables 36, 37 (page 39, rev C) agree with each other, and show that with an update rate of 8kHz, for example, you get a resolution of 14.4 bits (1.7uV) with a PGA of 64. (By the way, the sub-heading to these tables should surely read input voltage range, not noise?); table 46 on page 48 states that to get 8kHz update rate you set SF to zero. Does this mean that the sigma-delta converter is achieving the performance above using no decimation?