I am using two AD9914 DDS chips that are synchronized using the approach outlined in AN1254. They run on a 1.5 GHz reference clock, which should be low enough for successfull synchronization. Both chips are on the same PCB and receive their reference clock, as well as the IO_UPDATE signal through clock buffers and equalized length traces. The IO_UPDATE rising edge was carefully tuned to arrive exactly between rising edges of the SYNC_CLK at the DDS chips, so that no ambiguity can occur between the two AD9914 when sampling the IO_UPDATE signal.
Indeed, the SYNC_CLK of both chips runs with no phase offset after synchronization is complete. Also, when the same fixed frequency output signals are generated on both chips, they are in phase. Switching output frequency on the fly also does not break synchronization or phase relation.
However, synchronization does break, when ramp generation is attempted. Ramp generation was done as follows:
- Program all required ramp parameters (tested with and without AUTO CLEAR of phase and ramp counter)
- Use one of the following methods to trigger ramp generation:
+ Coincident IO_UPDATE at both DDS for writing a "1" to RAMP_EN bit.
+ Coincident toggling of DRCTL with RAMP_EN set to high before.
In both trigger variants for ramp generation, the output signals of the DDS chips are no longer in phase. Ramps are correctly generated but they are not synchronous. This is the case, because the SYNC_CLK of both DDS chips are also no longer in phase. Synchronization is effectively broken by triggering the ramp generator.
Why does ramp gerneration break synchronization? Also, how can this behaviour be mitigated?
Thanks in advance,