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AD9144: Lane Fifo Err and NCO ALIGNMENT with SYSREF

Question asked by Freddy_Y on Feb 20, 2018
Latest reply on Jun 21, 2018 by landsman

Hi,

AD91144 datasheet lists a start-up sequence consisting of step 1 to 6, it requires a SYSREF pulse (see datasheet page 25).

 

Question 1: after implementing the above procedure, JESD link is up but sometimes (5% of the times) LANEFIFOERR alarm shows up (reg 0x023 bit 1, Lane FIFO Error Status latched alarm when IRQEN_SMODE_LANEFIFOERR is high).

DAC is connected to an FPGA via JESD and both devices share the same clock, so I cannot understand why DAC FIFO goes empty/full.

Any clue on the root cause?

 

 

 

 

Question 2:

In order to enable Digital modulation (see page 68), we follow the basic start-up sequence consisting of step 1 to 6 requiring a SYSREF pulse (see datasheet page 25) and then we follow the NCO ALIGNMENT procedure (see page 70) using "SYSREF± alignment mode" which requires an additional SYSREF pulse.

Is it possible to send a single SYSREF pulse instead of 2 SYSREF pulses (one at startup and one for NCO alignment)?

 

Thanks,

Federico

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