I am wondering if anyone can help me regarding the AD JESD204b RX core developed by Analog Devices
1. AXI JESD204 RX core
The above link describes the AD AXI JESD204b Rx core. However, when I downloaded the source code, the verilog HDL code does not have the data in/out interface as following. There is NO RX_PHY ports and RX_DATA ports in the axi_jesd204_rx.v file. The lack of I/O interface can bee seen in the below link as well
I am wondering how can we use this core if it does not have input/output interface.
2. NON-AXI JESD204 RX core:
I also downloaded the non-AXI AD JESD20b core. I tested this core and found that it does not support the character alignment insertion function (FACI). Even thought it has scrambler module, but when I tested the JESD link with scrambler enabled, it failed. In summary, this non-axi core only works when the scrambling and FACI are disabled.
What are your thoughts about this?