I have been struggling to get two AD9915s on EVAL boards synchronized. The attached file shows my interpretation of the suggested circuit in AN-1254.
Basically, I have a programmable RF source at 2490 MHz. My output frequency is 2856 MHz through a high pass filter and amplifier chain for each AD9915.
I have no idea how you (whovever conceived the conceptual circuit) manage to get two CMOS outputs synchronized to the SYNC_CLK signal from what is shown in Figure 4 of AN-1254. I realize it is a conceptual circuit, but there is not enough of the concept illustrated.
Instead I developed my own circuit to make the leading edge of IO_UPDATE have a fixed time relation to SYNC_CLK. I am using a conventional dual D flipflop synchronizing circuit with two cascaded flipflops in a 74LVC74 with the raw IO_UPDATE on first D input. The output is buffered by a 74LVC132 configured as an inverter. This gives me 24 mA output and seems to be adequate two drive both EVAL boards through two 12" lengths of ribbon cable. The output indeed has a reliable fixed relation to the SYNC_CLK signal, and with a little timing adjustment, with both SYNC_CLK signals.
I have no problem setting the delays so that I can change the amplitudes, phases and frequencies of the two boards simultaneously while both outputs remain in sync with a fixed phase difference.
What i am unable to do is intialize both boards with the same phase. I have a subroutine to implement the sequence suggested in AN-1254, as best as I can interpret it. (There is a certain lack of clarity on the exact details.)
Each time I run the subroutine I get a different phase difference between the two outputs, no matter how I set the timing delays.
I also have a subroutine with which I am attempting to auto synchronously zero the phase advance registers, but everytime I run it the phase difference changes as well.
Maybe I have software issues. It's a little hard for me to tell.
It seeems to me that if I can change amplitudes, phases and frequencoes with a constant phase difference I am not too far from being able to get the **** things initialize to a constant phase difference. I am puzzled as to why I have a partial success. If I can't get the chip to start at a fixed phase difference, I ought to at least be able to align them by using the auto zero function for the phase advance registers. I have used this technique successfully to synchronize three AD9959 boards for a similar application. Generating a phase, ampltiude, and frequency adjustable output at 3 GHz from the AD9959 with a 500 MHz clock takes a bit of fancy rf circuitry. I went to the AD9915 to simplify the rf circuit. That part is great, but the problem of synchronizing two AD9915s has proven more difficult than expected.
Any advice from anyone who has succeeded in this task is greatly appreciated.