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Can't get the sampling rate in QPSK simulink example

Question asked by proxcmos on Feb 14, 2018
Latest reply on Feb 14, 2018 by travisfcollins

Hi

 

I'm trying to run the QPSK example provided in Simulink

 

here (MathWorks_tools/hil_models/qpsktxrx at 2015_R1 · analogdevicesinc/MathWorks_tools · GitHub )

 

I have modified it to run on AD9364

I had trouble understanding how to get lower Sample Rate 

which is the need for AD936x filter wizard

I have used the wizard to design a filter  as shown

 

And I click on "Coefficient to target"

 

The TermTerm shows

 

ad9361 spi32766.0: ad9361_calculate_rf_clock_chain: Failed to find suitable dividers: ADC clock below limit

 

 

 

Even though I get results but not sure if the ad9364 chip is configured well !! Is the sampling rate as the model shows which is 245.76 KSPS

 

 

 

Lower Constellation Diagram before freq/phase compensation and timing recovery .. upper is after 

 

I'm not sure if I am doing it right or I need to read more about AD9364 chip 

 

 

thanks

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