Are there any information about timing about input clock and Sync signal, and Sync signal and out put clock?
I received the quesion from out customer. I checked the datasheet but I couldn't find like that information.
Are you asking about any timing relationship between the input clock and the SYNCB signal? Are they interested in a setup and hold type number?
The SYNCB can be asserted either through the register map or via the SYNCB pin. The assumption on this signal is that it is asynchronous to the input clock, and therefore can occur at any time. The SYNC function is intended to align the common edges of the output clock when the output dividers have different divide values, or phase offset values.
While SYNC is asserted, the outputs are held low while the synchronization occurs. The SYNC signal is re-sampled by the input clock, which will avoid runt pulse generation. The internal timer will expire and release the reset on the output dividers simultaneously. The exact behavior of the outputs depends on the divide ratios, but for example, 2 channels setup with div2 and div4, the div2 channel will begin outputting pulses first, followed 2 cycles later of the higher rate clock, the div4 channel will being outputting pulses.
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