Are there any information about timing about input clock and Sync signal, and Sync signal and out put clock?
I received the quesion from out customer. I checked the datasheet but I couldn't find like that information.
The time period from when SYNCB arrives to when the output begins to toggle is deterministic based on the input clock. For a divide by 1 (bypass), it is 12 clock cycles from when SYNCB arrives to when the output begins to toggle. For more divide, the number of clock cycles increases, based on the divide ratio of all of the dividers. Also, if any phase adjust bits are used, this will change the time delay when the output begins to toggle.
This time to output is deterministic and does not vary with process, as the SYNCB signal is aligned to the input edge internally. All of the divide and phase adjust bits operate in the same deterministic way.
One thing I notice on the plot you provided, the SYNCB signal (red trace) has a very weak rising edge. This could cause some ambiguity on the input receiver. This may cause the SYNCB and input clock to become mis-aligned from SYNCB to SYNCB. I would recommend to use a buffer or increase the drive strength somehow to insure that the rising edge is faster.
Are you asking about any timing relationship between the input clock and the SYNCB signal? Are they interested in a setup and hold type number?
The SYNCB can be asserted either through the register map or via the SYNCB pin. The assumption on this signal is that it is asynchronous to the input clock, and therefore can occur at any time. The SYNC function is intended to align the common edges of the output clock when the output dividers have different divide values, or phase offset values.
While SYNC is asserted, the outputs are held low while the synchronization occurs. The SYNC signal is re-sampled by the input clock, which will avoid runt pulse generation. The internal timer will expire and release the reset on the output dividers simultaneously. The exact behavior of the outputs depends on the divide ratios, but for example, 2 channels setup with div2 and div4, the div2 channel will begin outputting pulses first, followed 2 cycles later of the higher rate clock, the div4 channel will being outputting pulses.
Thank you for your advice.
I would like to know a set-up hold time of SYNC to the input clock. And I also would like to know a time of the internal timer, which means a time of between SYNC and output. Could you please advise me about those times by actual value of designed value for a reference?
Thanks & Regards,
There really isn't a setup time for SYNCb. The outputs will go static immediately upon activation of SYNCb. The only time this may be an issue is if you want to be sure there aren't any runt pulses on the output.
As Steve mentioned, there is logic to prevent runt pulses on the deactivation of SYNCb.
Thank you for your answer.
Could you please refer following picture? Red line is SYNC, yellow line is input clock and green line and blue line are output clock by divider. Our customer concerns the period from sync to the output clock by divider. Can you inform us the time of the period? Does the time change by production lot? The customer needs to information about the time.
Thank you for your support!
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