I noticed that in FMComms2 ZC706 reference design, the DMA uses AXI3 protocol. In this design, I am going to include a custom IP created using Matlab HDL workflow advisor, between ADC FIFO and ADC Pack. However this IP has AXI4 slave/master interfaces. If I change the DMA controller from AXI3 to AXI4, how does that affect my design? Can you give me any suggestions to implement my requirement?