I hope this is the last question on the PLO circuit I designed.
As I said before, I use the HMC703LP4E and HMC509LP5, and the output frequency is 8185 MHz.
Before I say the problem, I will briefly describe the circuit I have designed.
The hardware configuration is as follows.
1. The SPI interface of the HMC703LP4E is connected to the FPGA.
However, the CEN pin is not connected to anything. In other words, the CEN pin is floating.
2. A 33-ohm damping resistor is connected in series between the SPI interface between the FPGA
and the HMC703LP4E.
3. The SPI interface between the current FPGA and the HMC703LP4E is 200 kHz.
This is because the EMI / RFI filter is applied to the power and SPI interfaces.
The problem is that the PLL is sometimes unlocked.
When the power is turned on and off repeatedly, sometimes it is unlocked.
When unlocked, the frequency is near 8800 MHz.
I know your answer to the previous question. your answer is "Also check the FPGA SPI signals (SCK, SDI, SEN) are not floating during power-on."
So I checked the SPI signal. There is no floating while the FPGA is booting.
I wonder what parts can be checked to solve this problem.