The ADAU1701 and ADAU1401 data sheets specify maximum SPI clock CCLK frequency as 6.25MHz.
The data is available on the COUT pin up to 101ns after the CCLK falling edge according to the table above, but the Figure 3 below clearly shows this delay as specified from CCLK rising edge.
The data sheet also states that: "COUT data is shifted out of the ADAU1401A on the falling edge of CCLK and should
be clocked into a receiving device, such as a microcontroller, on the CCLK rising edge."
For 6.25MHz clock with 50% duty cycle there is 80ns from falling clock edge to the rising edge. How the SPI interface could work with up to 101ns delay of the CDATA from the CCLK falling edge with the data being sampled by the microcontroller on the clock rising edges? Is the delay value correct?
According to the SPI timing diagrams either SPI mode 0 (CPOL = 0, CPHA = 0) or mode 3 (CPOL = 1, CPHA = 1) could be used for the ADAU1701 / ADAU1401 SPI accesses.
Could Analog Devices confirm the above.