Sigma DSP has noise reduction algorithm module for ADAU1761.
Unfortunately, it runs only for Fs=16kHz.
What’s need to be done to run it for Fs=48kHz.
The ADI NR algorithm runs at 16K because that's what the chip can handle. I've made several alternative NRs which run at 48K, using a frequency gating method. This splits the incoming audio into a number of frequency bands, gating each one ON only if its level is above threshold. Thus the scheme places "holes" in the response wherever the signal is insignificant -- which of course takes out the corresponding noise. Below is an example setup with three sections out of the total of 14 shown:
To design a frequency-selective noise gate like this, keep these principles in mind:
I'm on vacation so I could not test the attached project. It should run on a ADAU1761 eval board.
KJBob is correct in that there is not enough processing power to run it at 48kHz. However, these are only designed for audio used for voice communication systems which do not require full bandwidth. It is very difficult to design noise reduction that has a higher bandwidth. It requires very long FIR filters which will have a very long group delay so you will generally only see wideband noise reduction for system that process audio "off-line".
The spectral method KJBob suggested is one way to get some improvement.
Is your application for voice?
Thanks for your input on this interesting topic. I had assumed that since Mark prefers to run at 48K, he actually needed a wider signal bandwidth. On the other hand, the spectral technique also adapts to voice bandwidth simply by using closer-spaced, higher-Q filters at whatever sample rate. Several examples of this technique are scattered around the boards here. So far I haven't tried the ADI voice NR block -- does it use FIR (I see it includes a delay setting)?
I couldn’t reply to your posts last month.
Yes, this is voice related application and DSP is running as a slave from external clocks.
Also, I don’t have a lot of recourses left on this DSP and I can’t use larger chip because of the space constrains.
Looks like I have no choice and will implement a BPF.
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