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AD9652 - SFDR performance

Question asked by Se-woong on Feb 8, 2018
Latest reply on Feb 8, 2018 by PMH



My customer is considering to use AD9652 and they are testing the performance of AD9652 using AD9652 EVM (EVAL-AD9652).

On this  test, they got bad test result about SFDR values.

So they need your help for getting better SFDR values.

Please refer  below their test results and let me know your advices.


1.  The Performance Test configuration of AD9652

   A. Sampling Clock: 245.76MHz

   B. IF Frequency: 185MHz

   C. Frequency BandWidth: 100Mhz ( 135Mhz to 235MHz)

   D. Signal Input: Use SG (Signal Generater)


2.  Opinions from my customer abou this test result

   A. SFDR values are too small.

   B. It seems to be inserted Harmonics in used bandwidth.


3. Simulation Result using ADI Virtual Eval Tool-Beta

   A. Frequency : 195MHz

   B. Sampling Clock: 245.76MHz

   C. SFDR: 88 dBc


4.  Measured value on AD9652 EVM (EVAL-AD9652)

   A. Frequency : 195MHz

   B. Sampling Clock: 245.76MHz

   C. Input Power: 10dBm (Keysight Signal Generator EXG N5172B)

   D. SFDR: 59 dBc



Q1)   About above test result related SFDR,

      Would you suggest methods about removing sputious signals (second & third hormonics)  except using filters at ADC Input ?


Q2) About using LVDS signal at AD9652 Clock Input

     If they should use LVDS signals at AD9652 Clock Input, should they use AC coupled signals?

     If you have appropriate design example about this, please share this example to my customer.



Please advise me.