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AD9826 Bit Noise, ADClk, & Vref

Question asked by ead on Feb 6, 2018
Latest reply on Mar 7, 2018 by EBarnes

The ADClk signal seems to be coupling to VINR. The layout has these two traces on the opposite side of the 4 layer PCB. Any other ideas on how this can be removed?

 

Using the external reference the voltage difference (CAPB-CAPT) appears to be half of the range set to 4V or 2V (so capb-capt = 2V or 1V respectively). Shouldn't the voltage difference be equal to the range setting or is there some additional gain of 2 on the input signal? This is all with the gain set to 1.

 

Also is there a recommended value for CAPB and CAPT relative to the input signal? The video signal input level we have is about 300-760mV depending on the imaging device used. Previous posts seem to indicate it should be around the input signal level, but that doesn't seem to be the case here.

 

For both cases we are operating in 1-10 MHz range.

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