AnsweredAssumed Answered

Is it required to use the IDELAYCTRL and IDELAYE3 UltraScale primitives?

Question asked by beamer.ce1 on Feb 6, 2018
Latest reply on Feb 14, 2018 by beamer.ce1

Hi,

 

I have a design that utilizes the Xilinx UltraScale FPGA and using the 2016_r1 version of the HDL library and No-OS software

 

Since these primitives are not used by the digital tune function of the No-OS software to determine the clock and data delays, it is absolutely necessary to use the IDELAYCTRL and IDELAYE3 Xilinx UltraScale primitives to interface with a AD9361 with the 2016_r1 version of the HDL library?

 

Or can these primitives be bypassed and connect the rx_data and rx_frame differential signals directly from the AD9361 into the UltraScale FPGA without incurring any kind of unexpected consequences?

 

I look forward to your response.

 

- Brad

Outcomes