This reference is page30.
The AD9139 provides no a mode by which to MSPS the
clock cycles. latency variation only.
The innovative architecture of the AD9139 minimizes the
inherent latency variation. The worst-case variation in the
AD9139 is two DAC clock cycles. For example, in the case of a
1.6 GHz sample rate, the variation is less than 1.25 ns in any
Could you help me check the DAC Clock Cycles latency of AD9139?
Take AD9122 as example, it shows info below.