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ADV7482 driver development questions

Question asked by Hao_Arrow on Feb 6, 2018
Latest reply on Feb 16, 2018 by Poornima

Hi ADI support team,

 

We(our customer) have some technical questions for adv7482 driver development. Hope to get your kind advice. Thanks.

 

  1. We are not receiving SDP interrupts correctly, we have configured as below. We expect to see an unlock interrupt when the cable has been pulled out, and also interrupts regarding autodetection and lock state when signal is being locked onto. Is there any other requirement on setting up SDP interrupts or notes to consider? For reference the HDMI interrupt is working OK, and we have seen the SDP unlock interrupt work occasionally but not all the time.

 

/* Page name, Register, Mask, Value */

PAGE_IO, 0x75, 0x20, 0x20,    /* hdmi_encrpt_a_mb1 */

PAGE_IO, 0x75, 0x01, 0x01,    /* de_regen_lck_mb1 */

PAGE_IO, 0x47, 0x01, 0x01,    /* sd_int_mb1 */

PAGE_SDP, 0x0e, 0x00, 0x20,   /* SDP Map 1 */

PAGE_SDP, 0x44, 0x08, 0x08,   /* sd_unlock_mskb */

PAGE_SDP, 0x4c, 0x00, 0x0e,   /* sd_ad_chng_mskb, sd_h_lock_chng_mskb, sd_v_lock_chng_mskb */

PAGE_SDP, 0x0e, 0x00, 0x00,   /* ADI Required Write */

 

  1. To perform channel switching on the AFE side we change INSEL. After changing INSEL we are seeing a period of instability when enabling autodetection of SD modes. We are checking the in_lock signal to see that signal has been locked onto, and then query the detected video standard, however the standard is changing even though in_lock is constant. Is there any way to tell that the autodetect has completed and is stable other than polling? Snippet below from driver reading status 1, ad_result goes to PAL-60 -> NTSM-MJ -> PAL-BGHID (final and stable).

 

[ 1411.824911] adv748x 2-0070: status1 = 0x00000009

[ 1411.836095] adv748x 2-0070: status1 = 0x00000039

[ 1411.846023] adv748x 2-0070: status1 = 0x0000003d

[ 1411.856124] adv748x 2-0070: status1 = 0x0000003d

[ 1411.866194] adv748x 2-0070: status1 = 0x0000003d

[ 1411.876183] adv748x 2-0070: status1 = 0x0000003d

[ 1411.886144] adv748x 2-0070: status1 = 0x0000003d

[ 1411.896084] adv748x 2-0070: status1 = 0x0000003d

[ 1411.906191] adv748x 2-0070: status1 = 0x0000003d

[ 1411.916154] adv748x 2-0070: status1 = 0x0000003d

[ 1411.926081] adv748x 2-0070: status1 = 0x0000003d

[ 1411.936084] adv748x 2-0070: status1 = 0x0000003d

[ 1411.946176] adv748x 2-0070: status1 = 0x0000003d

[ 1411.956072] adv748x 2-0070: status1 = 0x0000003d

[ 1411.966078] adv748x 2-0070: status1 = 0x0000003d

[ 1411.976098] adv748x 2-0070: status1 = 0x0000003d

[ 1411.986265] adv748x 2-0070: status1 = 0x0000003d

[ 1411.996092] adv748x 2-0070: status1 = 0x0000000d

[ 1412.006143] adv748x 2-0070: status1 = 0x0000000d

[ 1412.016091] adv748x 2-0070: status1 = 0x0000000d

[ 1412.026266] adv748x 2-0070: status1 = 0x0000000d

[ 1412.036143] adv748x 2-0070: status1 = 0x0000004d

[ 1412.046143] adv748x 2-0070: status1 = 0x0000004d

[ 1412.056587] adv748x 2-0070: status1 = 0x0000004d

[ 1412.066732] adv748x 2-0070: status1 = 0x0000004d

[ 1412.076493] adv748x 2-0070: status1 = 0x0000004d

[ 1412.086576] adv748x 2-0070: status1 = 0x0000004d

[ 1412.096326] adv748x 2-0070: status1 = 0x0000004d

[ 1412.109796] adv748x 2-0070: status1 = 0x0000004d

[ 1412.126114] adv748x 2-0070: status1 = 0x0000004d

[ 1412.136073] adv748x 2-0070: status1 = 0x0000004d

[ 1412.146029] adv748x 2-0070: status1 = 0x0000004d

[ 1412.156239] adv748x 2-0070: status1 = 0x0000004d

[ 1412.166063] adv748x 2-0070: status1 = 0x0000004d

[ 1412.176040] adv748x 2-0070: status1 = 0x0000004d

[ 1412.186037] adv748x 2-0070: status1 = 0x0000004d

 

  1. We rely solely on main_reset i2c register value to reset the chip. I've found that one register at least is not being reset correctly through SW reset.

 

Example fl_enable register value in SDP MAP 2. 

 

/* Page name, Register, Mask, Value */

PAGE_SDP, 0x0e, 0x00, 0x40,   /* ADI Required Write */

PAGE_SDP, 0xe0, 0x00, 0x01,   /* fl_enable -> 1 */

PAGE_SDP, 0x0e, 0x00, 0x00,   /* ADI Required Write */

 

On main_reset, fl_enable register is still set to 1. On hardware reset the fl_enable register goes to 0 (as documented). Is this an erratum with the main_reset behavior and do we need to rely on hardware reset instead?

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