I’m using the AD9121-M5372-EBZ evaluation board connected by FMC with a ZedBoard. First of all I modify HDL reference design (ADFMCOMMS1) by deleting the ADC IP blocks from block design and change pinout on FMC Connector. The differences between both evaluation boards (AD9121 and FMCOMMS1) are mainly in connection number in FMC connector. I only want to send data samples from Linux to AD9121.
Some help including editing DTS and drivers were described in this post: AD9121-M5372-EBZ based on AD-FMCOMMS1-EBZ .
It seems that on the I/Q outputs of the AD9121 evaluation board there is some data, and after I made some changes in code it changing the output, but unfortunately I can't force DAC to get reasonable data e.g. the square/sawtooth wave. The 500 MHz reference clock is supplied to the DAC. I have set the options from PC:
PLL is indicating as locked. However when registers are read from the DAC, there is some Warning 1 and Warning 2 of FIFO appearing - I think its the result of my problem.
I have checked almost everything in project:
- FGPA (especially the pin mapping and DMA addressing),
- the clocking signals (I checked that DCI/DACCLK signals are synchronized and seems that they are ok).
But when I checked the signals in FMC connector lines it seems that they are not working properly when the signal is changing through time (only first two bits seems working properly when I implemented simple counter).
However, they have correct states when I put static values into the buffer (e.g. buffer of 1024 samples, all of them are 0x01 or 0x02 etc.) - that proves that pins maping is correct in HDL project.
Do someone have any idea where the problems is?