AnsweredAssumed Answered

Link error

Question asked by JanBilek on Feb 5, 2018
Latest reply on Feb 20, 2018 by PMH

Hi,

 

we are building a system consisting of a carrier board (our design) with Xilinx Ultrascale FPGA and a mezzanine card (FMC, also our design) with AD6676. We are currently testing our ADC board using Virtex and KU eval boards since we don't have our carrier board yet. And we are facing some issues with JESD communication. And so I would like to kindly ask you for your support to solve our problem.

 

Problem statement:
Time to time the Xilinx JESD core reports following Link errors:

-Disparity Error(s) received

-Not in Table Error(s) received

Total sum of these errors (provided by "Link Error Count" counter) is around 5000 per hour when using original ADI AD6676 EVM. But unfortunately it is much higher with our ADC board.

On the other hand, inside the FPGA we are continuously checking the ramp signal received from the AD6676 and we se almost no errors there! Just one sequence of around 100 samples is wrongly received per 3-5 hours of continuous run.

So it seems - when looking at the ramp received - that the setup works fine. Both with the original ADI AD6676 EVM and with our ADC board. But we are confused with the errors reported by the JESD core.

Both FPGAs (on the KU040 and VC707) gives similar results

 

Conditions and Configuration:
So far we are using KU040 and VC707 eval kits together with AD6676 EVM or with our own ADC board. Test signal used: RAMP generated by the AD6676.

Note that we use bare JESD core without any extensions (that are provided inside the ADI reference design).

 

Configuration:

Xilinx JESD204 7.1

Subclass 1

Scrambling on

L=1

F=4

K=32

LMFC Buffer Size = 1024

Include Shared Logic in core

Transceiver Type GTHE3

Line Rate 4,9152 Gbps

Reference clock 122,88 MHz

PLL Type CPLL

DRP Clock Frequency 100 Mhz

 

AD6676 JESD config

0x1C0 JESD204 DID: 0x1

0x1C1 JESD204 BID: 0x5

0x1C3 JESD204 L/SCR: 0x80

0x1C4 JESD204 F: 0x3

0x1C5 JESD204 K: 0x1F

0x1C6 JESD204 M: 0x1

0x1C9 JESD204 S: 0x0

0x1D0 JESD204 LID0: 0x0

0x1D1 JESD204 LID1: 0x1

0x1D8 JESD204 FCHK0: 0x44

0x1D9 JESD204 FCHK1: 0x45

0x1E0 Enable Lane FIFO: 0x1

0x1E1 Swap: 0x0

0x1E2 Link/Lane Power-Down: 0x0

0x1E3 Interface Control 0: 0x14

0x1E4 Interface Control 1: 0x0

0x1E5 Interface Test: 0x7

0x1E6 ILAS Count: 0x0

0x1E7 SYNCINB and SYSREF Control: 0x4

0x1E8 Clock Synchronization: 0x4

0x1E9 LMFC Offset: 0x0

0x1EA SYSREF Window: 0x0

0x1EB PHY Control 0: 0x1C

0x1EC PHY Control 1: 0xBD

0x1EF PHY Control 3: 0x0

 

Any idea why we are getting so many of these error messages? Could that be a HW problem? Or problem with SW configuration?

 

I'd appreciate any help in that.

Regards,

Jan.

Outcomes