AnsweredAssumed Answered

AD9915 linear sweep timing is incorrect

Question asked by p_lauria on Feb 2, 2018
Latest reply on Feb 6, 2018 by mcee

I am running the evaluation board and running a linear sweep using the digital ramp generator. The sweep is running in with the bits set for no-dwell high and no-dwell low (i.e. continuous ramp), but I don't seem to be able to make sense of the timing.

 

I am running with a 2.5GHz clock, and my sweep range is 79 MHz to 81 MHz.

 

I set the slope step interval to be 9.6 ns (i.e. the minimum it can be, fs/24).

 

So, for the slope step interval, I send to the DDS (over SPI in MSB-first):

 

[8, 0, 1, 0, 1] (dec)

 

For the frequency step, I want 384 Hz. So, since df = (M / 2**32)*sysclk, M=660 (0x294) :

 

[6, 0, 0, 2, 148] (dec)

[7, 0, 0, 2, 148] (dec)

 

So you can see that both the rising- and falling step sizes are the same.

 

The only other register I write to next is the ramp register (where I enable the ramp and DROVER outputs):


 [0x01, 0x00,0x0e,0x29,0x00]

 

With a 2MHz sweep range, and a 9.6ns step size, then NUM_STEPS = abs(startfreq - stopfreq)/STEP_SIZE, I calculate the sweep should take *exactly* 50us to get from one frequency to the next.

However, when I monitor DROVER on a scope, I find the exact spacing to be 33 us! I've been scratching my head about this for days, trying different steps sizes and times, but the timing always seems to be about 40% off.

 

Can someone please explain what I am doing wrong?

 

(The only other initialization I do which I omitted, was set the  DACCAL bits high and low, as required.)

 

Thanks!!!

Outcomes