We have a design where we are using two serial lanes with both RX/TX 1 & 2 enabled. Our TX path looks great, no issues. Unfortunately our RX path seems to have an issue. It looks like the framer is copying the same data to both serial lanes. We were given a digital loop back python command that allows the framer to get it's data from the deframer instead of the ADC path. FYI our sample rates and lane rates are the same.
I have collected the samples inside my FPGA and it appears that the data is being copied from TX serial lane 1 to both RX lane 1 and 2. I have tried using the framer in auto mode and in manual but we get the same result.
We have also manually enabled the RX/TX paths using the GPIO rx_enable/tx_enable pins with no luck.
Could you please help find a solution?