I am working with the AD9914/AD9915 chip, attempting to synchronize the leading edge of the IO_UPDATE pulse with the SYNC_CLK. I am using two cascaded D flip-flops with the raw IO_UPDATE signal on the first D input. The SYNC_CLK signal drives the CLK input of both chips. This should provide an IO_UPDATE output with both leading and trailing edges synchronized with the SYNC_CLK. However, there is a catch. The rising edge of the output is indeed fixed with respect to the SYNC_CLK. However, as soon as the IO_UPDATE goes high the SYNC_CLK disappears. The output pulse seems to reset after about 1 ms. I though I would be able to control the lenght of the IO_UPDATE pulse by the length of the input pulse. Will I have to reset the flip flops myself to keep from having a really long output pulse?