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How to improve the EZ-KIT BF548 NOR Flash read speed ?

Question asked by BFProgrammer on Nov 24, 2011
Latest reply on Nov 28, 2011 by BFProgrammer

Hi All!

We want to improve at maximum the read speed of "Intel StrataFlash Embedded Memory (P33)".

So, we choosed the most fast access mode - the Burst Mode:

 

Follows the function from VisualDSP++ package I found that set the flash burst mode:

 

ERROR_CODE SetToBurstMode( unsigned long lBurstClock,
       unsigned char chAccessTime,
       unsigned char chHoldTime,
       unsigned char chSetupTime)
{
    u16 uwRCRtmp;
    u16 uwRCR_Default;

    // disable the Async Memory
    *pEBIU_AMGCTL = 0x0000;
                   
    // Set the mode to async Mode (0-async mode, 1-flash mode, 2-page mode, 3-burst mode)
    *pEBIU_MODE   = ( B0MODE_BURST | B1MODE_BURST | B2MODE_BURST | B3MODE_BURST );

    *pEBIU_FCTL   = lBurstClock;
   
   
*pEBIU_AMBCTL0 =  0xffc2f002 | (chAccessTime << 8) | (chHoldTime << 6) | (chSetupTime << 4) ;   
   
   
    *pEBIU_AMGCTL = ( AMCKEN | AMBEN );     /* enable the Async Memory */
    ssync();

    //RCR : Read Configuration Register
    //Configuring the RCR enables synchronous burst-mode reads.
    uwRCR_Default = 0xBFCF;                    /* hardwired to facilitate the test , it may be GetRCR( &RCR_Default ); */
    uwRCRtmp = uwRCR_Default & 0x05F0;
    uwRCRtmp |= 0x0003;
    uwRCRtmp |= 3 << 11;
    SetRCR ( uwRCRtmp );
   
    ResetFlash();

    return NO_ERR;
}

 

This function works for some slow default parameters:

 

//Default: Burst clock=SCLK/4, 0xF accesstime=15cycles,HoldTime=3cycles,SetupTime=0 (4cycles)
    SetToBurstMode(BCLK4,0xF,3,0);

 

When I change the Burst clock to SCLK/3 and Setup Time to 2 cycles (as recommended by HRF), the flash read fails and flash gets corrupted.

I test it on ADI EZ-KIT BF548, that has the following default clocks:

CCLK=525MHz, SCLK=131.25., CLKIN=25MHz

 

So my question is what is the limit configuration of NOR Flash, that set it to maximum read speed.

 

Peter.

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