I am trying to configure the BCLK and LRCLK for the SSM3582 eval board. The device is used as a slave to an ARM based board via I2S. So far, I got some relatively good results but it's far from perfect.
If I understood correctly, the goal is to get LRCLK to match the sample rate of the file we're playing.
Also, BCLK must be greater than 2.048 MHz. Is there a higher limitation ?
Finally, just to be clear, LRCLK = FSYNC, right ?
Here's how I make my calculations. Hopefully someone will be able to highlight my mistake(s).
1) From the audio file, I get the sample rate (44100 Hz in this case).
2) From the ssm3582 datasheet, table 13, I pick a BCLK/FSYNC ratio that support that sample rate, say 192.
3) BCLK is supposed to be (sample rate) x (ratio) so 44100x192 = 8 467 200 Hz. My ARM ss0 peripheral clock being 100 MHz, I get a divider value of 6 to get as close as possible to the required BCLK value. With DIV = 6, I end up with a BCLK = 8 333 333 Hz.
4) Now that I have BCLK, I can get LRCLK using FSYNC = BCLK / (2x(PERIOD+1)). I endup with PERIOD = 93 which gives me a FSYNC clock frequency of 44.3kHz.
So, when using those value with a 44100Hz Stereo MP3, I actually get no sound on either channel. To get audio, I need to adjust FSYNC to 43.4KHz (without modifying BCLK) and then I get good quality audio on the right channel, and bad audio with noise on the left channel BUT music is too slow. Not by much, but still, it's slow enough that we notice.
Any idea what it is I'm doing wrong ?