I am currently employing AD9650 to sample IF signals of 15.3MHz. The ADC font-end follows the AD9650 datasheet design using transformer coupling (see the attached shematic). The sampling clock is differential at 50MHz with low jitter. No explicit noise sources near the ADC. However, the SNR of directly sampled signals is calculated as 60dBC, and the SFDR is 68dBC. The result is far away from the expected object. Can I get any advice of improving the ADC SNR?