AnsweredAssumed Answered

AD9914 DRG

Question asked by waderose on Jan 31, 2018
Latest reply on Feb 5, 2018 by mcee

ADI engineers, I recently used AD9914 to achieve the function of sweep frequency, but after the power on, there is only the lower limit output. Please have a look, answer for me, the system clock is 2.5GHz, and hope to achieve 100MHz-200MHz sweep function.

The register settings is not changed,like this:

CFR1=0x01010308

CFR2=0x008AA800

CFR3=0x00041927

CFR4=0x01052120

Digital Ramp Lower Limit=0x0A3D70A3(register address is 0x04,100MHz)

Digital Ramp Upper Limit=0x147A1E47(register address is 0x05,200MHz)

Rising Digital Ramp stope=0x0000431C(register address is 0x06,10kHz)

Falling Digital Ramp stope=0x0000431C(register address is 0x07,10kHz)

Digital Ramp Rate Register=0x00870087(register address is 0x08,1.3us)

Profile 1=0x0E660000(0x0E,Amplitude factor 0.9)

After I write data, I can make the DRCTL pin switch on high and low level, a pulse is 8.2ms, and the interval between each pulse is 8.2ms, and a sweep cycle is 13ms. After setting a no_dwell high level, it seems that we can finish a sweep cycle.So I don't know where there's a problem.

In addition, the DROVER pin has been high level to prove that the function of sweep frequency is not realized.

And DROVER, DRHOLD, the two pins on the default is the default is high?The DRHOLD pin should be set to a low level, right?

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