I need to read a 100Msps 12-bit ADC into an SC582 or SC584 continuously. It looks like the maximum EPPI transfer rate (whilst generating clock and frame) is 75 Mwords per second which is not fast enough for a straightforward ADC interface.
If I use an FPGA to generate 24-bit words (2x12 bit samples), could I use the EPPI/DMA to unpack that data into a 16-bit buffer in SHARC L1 memory at 100Mwords/second (ADC rate) or 50Mwords per second (EPPI clock) rate?
Eventually I want to end up with sequential ADC samples in 32 bit floating point format to DMA into the FFT acelerator but I might have to do a manual 16-bit integer to 32-bit float translation first. The latency isn't very ipotant but the throughput is.
I think the EPPI / DMA would have to be in General purpose 1 Frame Sync mode.
According to the datasheet (Table 18-49), if DLEN is 24 and SPLTWRD is 1, it looks as though it might be possible.
Does anyone understand the datasheet well enough to know if this is correct?