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AD9528 Device Tree NDIV

Question asked by dasiagi on Jan 30, 2018
Latest reply on Feb 5, 2018 by mhennerich

On the ADRV9371 card I have changed some capacitors/resistors so that the on board VCXO does not connect and the REF CLK SMA instead is routed through to VCXO_IN on the AD9528. This worked fine while I fed in a 122.88 MHz clock. Now I would like to  change this so that I can instead feed in a 100 MHz clock.

 

In the device tree there are two entries which seem relevant:

 

clocks{

   #clock-cells = <0x0>;

   compatible = "fixed-clock";

   clock-frequency = <0x989680>;

   clock-output-names = "ad9371_ext_refclk";

};

 

                        ad9528-1@0 {
                                #address-cells = <0x1>;
                                #size-cells = <0x0>;
                                #clock-cells = <0x1>;
                                compatible = "ad9528";
                                spi-cpol;
                                spi-cpha;
                                spi-max-frequency = <0x989680>;
                                reg = <0x0>;
                                clock-output-names = "ad9528-1_out0", "ad9528-1_out1", "ad9528-1_out2", "ad9528-1_out3", "ad9528-1_out4", "ad9528-1_out5", "ad9528-1_out6", "ad9528-1_out7", "ad9528-1_out8", "ad9528-1_out9", "ad9528-1_out10", "ad9528-1_out11", "ad9528-1_out12", "ad9528-1_out13";
                                adi,vcxo-freq = <0x7530000>;
                                adi,refa-enable;
                                adi,refa-diff-rcv-enable;
                                adi,refa-r-div = <0x1>;
                                adi,osc-in-cmos-neg-inp-enable;
                                adi,pll1-feedback-div = <0x4>;
                                adi,pll1-charge-pump-current-nA = <0x1388>;
                                adi,pll2-ndiv-a-cnt = <0x2>;
                                adi,pll2-ndiv-b-cnt = <0x7>;
                                adi,pll2-vco-diff-m1 = <0x3>;
                                adi,pll2-n2-div = <0xa>;
                                adi,pll2-r1-div = <0x1>;
                                adi,pll2-charge-pump-current-nA = <0xc4888>;
                                adi,sysref-src = <0x2>;
                                adi,sysref-pattern-mode = <0x1>;
                                adi,sysref-k-div = <0x200>;
                                adi,sysref-request-enable;
                                adi,sysref-nshot-mode = <0x3>;
                                adi,sysref-request-trigger-mode = <0x0>;
                                adi,rpole2 = <0x0>;
                                adi,rzero = <0x7>;
                                adi,cpole1 = <0x2>;
                                adi,status-mon-pin0-function-select = <0x1>;
                                adi,status-mon-pin1-function-select = <0x7>;
                                reset-gpios = <0x4 0x71 0x0>;
                                linux,phandle = <0x8>;
                                phandle = <0x8>;

                                channel@13 {
                                        reg = <0xd>;
                                        adi,extended-name = "DEV_CLK";
                                        adi,driver-mode = <0x0>;
                                        adi,divider-phase = <0x0>;
                                        adi,channel-divider = <0xa>;
                                        adi,signal-source = <0x0>;
                                };

 

So, since channel-divider = 0xa, that is why clock-frequency is 12288000, so I would want that to change to 10000000.

 

Regarding the AD9528 entry though, I am confused. Using [this](https://ez.analog.com/docs/DOC-16454-ad9371-evaluation-board-vcxo-selection) document, I believe these values should get me a device clock of 80 MHz with a 100 MHz input clock:

 

M1 = 3

N2 = 120

R1 = 10

chDIV = 15

 

The relevant available parameters are

 

                                adi,pll2-ndiv-a-cnt = <0x2>;
                                adi,pll2-ndiv-b-cnt = <0x7>;
                                adi,pll2-vco-diff-m1 = <0x3>;
                                adi,pll2-n2-div = <0xa>;
                                adi,pll2-r1-div = <0x1>;

 

I understand the latter 3, but what is the function of pll2-ndiv-a/b-cnt? How do I determine what values to set for these?

 

And will I need to change anything other than the device tree entries mentioned here? Are there any constraints on what the other clocks, FMC_CLK,DEV_SYSREF,FMC_SYSREF, need to be?

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