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ADuCM3029: ACLK value

Question asked by tdezotti on Jan 30, 2018
Latest reply on Feb 1, 2018 by tdezotti

Hi,

 

I want to configure the internal ADC of the ADuCM3029, but I have some questions about ACLK.

 

1. In the document ADuCM302x-mixed-signal-control-processor-hardware-reference.pdf, page 6-22, Table 6-9, it is said that ACLK default value is 6.5 MHz, but in Figure 6-12, it is said that ACLKDIVCNT is 0x10 = 16, so ACLK is 26 MHz/16 = 1,625 MHz. When I see this register in CrossCore, ACLKDIVCNT = 0x10. What is the default value of ACLK?

 

2. In the same document, page 6-4, it is said "The frequency of PCLK must be less than or equal to the frequency of HCLK, and the ratio of the dividers must be an integer." Is there some relation between ACLK and PCLK? ACLK can be greater than PCLK and HCLK?

 

3. I want to configure PCLKDIVCNT = HCLKDIVCNT = 0x02 (26 MHz/2 = 13 MHz) and ACLKDIVCNT = 0x01 (26 MHz). Is there a problem? Will the internal ADC work using this values?

 

Thanks.

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